1. Technical Field
The present invention relates to a solid-state image capturing device and an image capturing apparatus, for performing one-line compression.
2. Background Art
The number of pixels is already exceeds 10 millions in a digital still camera while exceeding 20 millions in a digital single-lens reflex camera, and this trend is expected to continue. There is also an increasing demand to enhance a frame rate in capturing a moving image. For the two reasons described above, various techniques are studied to meet a demand for significantly high speed data output in a solid-state image capturing device that is of a key part of a camera system.
A physical method for dealing with speed enhancement of data transfer includes only extension of an output terminal and speed enhancement of a data transfer frequency. However, unfortunately a circuit scale of the solid-state image capturing device is enlarged in the method for increasing the number of output terminals. In the method for increasing the data transfer frequency, problems of an electromagnetic noise and timing skew during signal passing between semiconductor elements are generated because of an increased operating frequency of a circuit. Additionally, power consumption is increased in both the methods, and therefore a problem of degradation of an image capturing characteristic is generated in the solid-state image capturing device.
Data compression also exists in the method for effectively achieving the speed enhancement of the data transfer, not depending on the physical countermeasure. A method in which a two-dimensional discrete cosine transform circuit and a one-dimensional Huffman coding circuit are mounted has been proposed in the solid-state image capturing device (for example, see Unexamined Japanese Patent Publication No. 2003-234967).
Hereinafter, a solid-state image capturing device of the background art will be described with reference to the drawing.
FIG. 30 is a block diagram illustrating a configuration of the image capturing apparatus of the background art.
Referring to FIG. 30, after performing a read scan for each row of a pixel array configured by 512 by 512, analog pixel signals read from a pixel array are stored in analog buffer 910c, A/D conversion is performed by A/D conversion circuit 911, two-dimensional discrete cosine transform (hereinafter referred to as a DCT) is performed in each four blocks by compression circuit 912 with 4×4 pixels as one block, and one-dimensional Huffman coding is performed to a calculation result of the two-dimensional DCT, thereby performing the compression of the pixel data.